CV / English / RTL Design Engineer
Alex Riviera
- Phone: +1 234 567 890
- Email: [email protected]
- LinkedIn: linkedin.com/in/alexriviera
- Address: 123 Silicon Valley, Sunnyvale, CA, 94086
Brief
Adept RTL Design Engineer with over 5 years of experience in designing and verifying complex digital circuits. Specializes in writing efficient, scalable Verilog and SystemVerilog code for FPGAs and ASICs. Proven track record of optimizing designs for performance and power consumption, while ensuring functional correctness through rigorous simulation and testing. Passionate about keeping abreast of the latest industry trends and technologies.
Core Competencies
- Digital Circuit Design
- RTL Coding (Verilog & SystemVerilog)
- FPGA and ASIC Design Flows
- Functional Verification
- Performance Optimization
- Power Consumption Analysis
- Debugging and Simulation Tools
- Cross-functional Team Collaboration
- Agile and SCRUM Methodologies
Technologies and Certifications
- Languages: Verilog, SystemVerilog, VHDL
- Tools: Xilinx Vivado, Intel Quartus, Cadence Incisive, Synopsis VCS, ModelSim
- Certifications: Certified ASIC Verification Engineer (CAVE), Advanced FPGA Design Certification
Professional Experience
Senior RTL Design Engineer
MicroTech Solutions Inc., San Jose, CA Jan 2019 - Present
- Led the design and verification of a high-performance network processor, resulting in a 20% improvement in throughput.
- Collaborated with the architecture team to define specifications and develop scalable hardware solutions.
- Implemented power-saving features that reduced overall power consumption by 15% without compromising on performance.
Junior RTL Design Engineer
Innovative Circuits Inc., Austin, TX Jul 2015 - Dec 2018
- Contributed to the development of a multi-core processor design, focusing on optimizing interconnect and memory access.
- Assisted in the verification of digital blocks using SystemVerilog and UVM, identifying crucial bugs early in the design cycle.
- Participated in the full product lifecycle, from specification through to manufacturing support.
Education and Training
- M.S. in Electrical Engineering, University of California, Berkeley, 2015
- B.S. in Electronic Engineering, Texas A&M University, 2013
Workshops and Seminars
- Advanced Verilog for Verification, 2017
- Low Power Design Techniques, 2018
Referees
Available upon request.